1. Field of the Invention
This invention relates to analog-to-digital converters. More specifically, this invention relates to integrating type analog-to-digital converters, and in particular, dual slope integrating converters.
2. Description of the Prior Art
An analog-to-digital (A/D) converter provides a digital output which indicates the magnitude of an unknown analog input signal. The output may be a decimal number such as "4.25" or a binary number such as "10.01" which signifies some multiplier times a standard unit such as the "volt".
Heretofore, two types of analog-to-digital converters have been used, each having particular advantages and disadvantages. The two types are referred to as successive approximation type and integrating type converters. A successive approximation analog-to-digital converter employs a digital-to-analog converter (DAC) in a feedback loop with a comparator and a logic circuit referred to as a "successive approximation register." In the standard system, a binary sequence is employed. Initially, the most significant binary bit (MSB) is set to one, and all lower bits are set to zero. The DAC then produces an analog voltage corresponding to the value of that most significant bit. For example, in a ten-bit system, the DAC initially might produce a voltage of 2.sup.9 =512 volts. If this voltage is less than the analog input, the MSB is left at one. If the DAC output is greater than the input, the bit is set to zero.
The successive approximation register then moves on to the next bit of lower significance. This bit is set to one, and the resultant DAC output again is compared to the unknown analog input. If the DAC output is less than the input, this bit is left at one; if not, the bit is set to zero. The process is repeated successively for all bits. At the completion of the conversion, those bits left in the one state produce an output voltage from the DAC which would match the analog input to within + or - 1/2 of the least significant bit. Performing an "n" bit conversion requires only "n" trials, making the technique capable of high speed conversion.
In the conventional successive approximation converter employing a binary sequence, the digital-to-analog converter uses an impedance network in which the elements correspond to values of the binary sequence. For example, the DAC may employ a set of resistors which are selected to produce voltages or currents having values of 512, 256, 128, 64, 32, 16, 8, 4, 2 and 1. While successive approximation analog-to-digital converters are very fast, they are also complex and it is difficult to achieve 12 bit accuracy with present chip technology. The resistors in the impedance network invariably have to be trimmed by laser trimming or otherwise to achieve the desired accuracy. Even then, a significant percentage of the resistors do not meet the accuracy requirements.
Compared to a successive approximation converter, the integrating type analog-to-digital converter is simple, low cost, very linear and slow. Generally, its speed is limited to approximately 100 readings per second to achieve 12 bit accuracy as opposed to 50,000 readings per second for a typical IC successive approximation converter. In a dual slope integrating analog-to-digital converter, an analog input signal is integrated for a fixed period of time. The integrator is then discharged at a known rate until its output crosses zero, with zero crossing being detected with a comparator. This is shown in FIG. 2 of the drawings. The first phase is an "auto-zero" phase, which corrects for offset voltages of the analog components of the converter. The ratio of the integrating time (phase II) to the discharge time (phase III), which can be measured digitally (i.e., by counting clock pulses), is proportional to the value of the analog input signal.
The major drawback of the dual slope integrating analog-to-digital converter is its relatively slow speed. This slow speed has been necessitated by the need to obtain high accuracy discharge time measurements, i.e., to accurately measure the zero-crossing of the integrator. Since clock pulses are counted to determine the discharge time, one or more clock pulses is required for each quantum of measurement. For example, a 12 bit converter requires at least 2.sup.12 or 4096 clock pulses of deintegration per measurement if the least significant bit is to be accurate. Additional time (approximately another 4096 pulses) is required for the auto-zero and integrate phases.
Since the minimum number of clock pulses per measurement in prior art converters is controlled by the quantum of measurement, it is apparent that the speed of a measurement cycle can only be increased by using a fast, i.e., high frequency clock. However, the use of a fast clock is limited by the delay of the comparator in detecting zero crossing. In order to obtain an accurate count of the deintegrate time, the comparator delay should be no more than one-half clock pulse. The comparator used in one typical prior art converter has a 3 .mu.s delay in detecting zero crossing. Using the one-half clock pulse delay criterion, the clock frequency with this converter is limited to 160,000 KHz or approximately 20 readings per second for a 12 bit converter.
It is a primary object of the present invention to provide an integrating analog-to-digital converter which achieves high accuracy while at the same time being very fast, i.e., having a very short measurement cycle.
It is another object of the present invention to overcome the comparator delay and fast clock requirement limitations of prior art converters.
It is a further object to provide a converter which requires less than 200 clock pulses for a 12 bit conversion as opposed to more than 8,000 required in prior art converters.
It is yet another object of the present invention to provide a converter which does not require at least one clock pulse of deintegration per quantum of measurement.